The present invention relates generally to electronic device testing and verification, and, more particularly, to a method and system for estimating capacitive coupling between signals in a hierarchical design.
In integrated circuits, wiring boards, or any electronic circuitry, there is a capacitance between signal lines and other signal lines, and between signal lines and ground. The capacitance between signal lines and ground is sometimes referred to as xe2x80x9cgoodxe2x80x9d capacitance as it reduces cross-talk between signal lines. This good capacitance may exist between signal lines and the substrate upon which the circuitry is formed, between signal lines and transistor gates, and between signal lines and diffusion regions. Cross-talk can be thought of as interference to a signal imparted to that signal by a signal coupled to it from another conductor.
The capacitance between signal lines and other signal lines is sometimes referred to as xe2x80x9cbadxe2x80x9d capacitance. This bad capacitance capacitively couples signals on respective wires and increases the likelihood of cross-talk between the capacitively coupled signal wires. Some signal to signal capacitance can be considered good capacitance, if, for example, it does not add significantly to the worst case noise event on the subject signal.
During the design and testing of electronic circuitry, it is desirable to have the ability to determine the total capacitance affecting each signal in the design and the ability to distinguish between capacitance to ground and coupling capacitance between signals. The total capacitance is the total of the good capacitance (between the subject signal and ground) and the bad capacitance (between the subject signal and other signals capacitively coupled to the subject signal). In particular, it is important to know the bad capacitance (capacitive coupling) affecting each signal in the design.
One manner to determine the capacitive coupling onto each signal in a design is to consider each of the aggressor signals individually, so that each victim is analyzed multiple times for the effects of capacitive coupling. As used in this document, a signal is considered a victim when it is being analyzed to determine the signals (aggressors) that are capacitively coupled to the victim. This requires that these multiple analyses be combined in some way to demonstrate that there is not a problem with capacitive coupling in the design. Unfortunately, this approach is inefficient and consumes valuable processing resources.
Another manner in which to determine the capacitive coupling onto each signal in a design is to decide, at the child level of the design, whether an aggressor presents good capacitance or bad capacitance to the victim, instead of at the top level of the design. A design may have a number of child levels that are included in a parent level of the design. Unfortunately, this approach ignores the additive effects of each child group in the design and the parent.
Yet another manner in which to determine the capacitive coupling onto each signal in a design is to extract each capacitance in the design and consider each extracted capacitor individually for the good capacitance/bad capacitance determination. This should be done without adding the entire capacitance between an aggressor and its victim. Unfortunately, because typical capacitor extraction programs do not combine the capacitances in a single level, let alone across a hierarchy, this approach ignores the total capacitance between signals, in the good capacitance/bad capacitance determination.
Therefore, a need exists for an efficient, simple way to determine total capacitance in an electronic design, and to distinguish between capacitance to ground (good capacitance) and capacitive coupling (bad capacitance) to other signals.
The invention provides a system and method for estimating capacitive coupling between signals in a hierarchical design.
The present invention may be conceptualized as a method for estimating capacitive coupling in a hierarchical design. The method comprises the steps of providing a circuit having a first level and a second level, providing a first signal in the circuit, providing at least one additional signal in the circuit, the additional signal coupled to the first signal, determining a coupling capacitance between the first signal and the additional signal, the coupling capacitance determined with respect to the first level, resulting in a first level coupling capacitance, and with respect to the second level, resulting in a second level coupling capacitance, and adding the first level coupling capacitance to the second level coupling capacitance to determine a total coupling capacitance between the first signal and the additional signal.
Architecturally, the present invention can be conceptualized as a system for estimating capacitive coupling in a hierarchical design, comprising a circuit having a first level and a second level, a first signal associated with the circuit, at least one additional signal associated with the circuit, the additional signal coupled to the first signal, logic configured to determine a coupling capacitance between the first signal and the additional signal, the coupling capacitance determined with respect to the first level, resulting in a first level coupling capacitance, and with respect to the second level, resulting in a second level coupling capacitance, and logic configured to add the first level coupling capacitance to the second level coupling capacitance to determine a total coupling capacitance between the first signal and the additional signal.
The invention has numerous advantages, a few of which are delineated, hereafter, as merely examples.
An advantage of the invention is that it quickly and efficiently determines the total capacitance in a hierarchical design.
Another advantage of the invention is that it determines between effective capacitance to ground and relevant coupling capacitance to other signals in the design.
Another advantage of the invention is that it can determine the weighted average of the rise or fall times of all signals capacitively coupled to a subject signal.
Another advantage of the invention is that it is simple in design and easily implemented on a mass scale for commercial production.
Other features and advantages of the invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. These additional features and advantages are intended to be included herein within the scope of the present invention.